FPGA开发资料

计算器
全加器电路的VHDL程序
--fadd.vhd fadd.vhd one bit full adder
library ieee;
use ieee.std_logic_1164.all;
entity fadd is
port( a: in std_logic;  --被加数
         b: in std_logic; --加数
         ci: in std_logic;
         sum: out std_logic;
         co: out std_logic);
end fadd;
architecture behavior of fadd is
begin
co<=(a and b) or (b and ci) or (a and ci);
sum<=a xor b xor ci;
end behavior;

全加器电路的组件定义
library ieee;
use ieee.std_logic_1164.all;
package components is
component fadd
port(a: in std_logic;  
         b: in std_logic;
         ci: in std_logic;
         sum: out std_logic;
         co: out std_logic);
end component;
end package;

四位逐位进位加法器电路VHDL程序
--fadd4.vhd 4-bit ripple-carry adder
library ieee;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port( a: in std_logic_vector(3 downto 0);
        b: in std_logic_vector(3 downto 0);
        ci: in std_logic;
        co: out std_logic;
        sum: out std_logic_vector(3 downto 0));
end fadd4;
architecture behavior of fadd4 is
signal ci_ns : std_logic_vector(2 downto 0);
begin
u0: fadd port map(a(0),b(0),ci,ci_ns(0),sum(0));
u1: fadd port map(a(1),b(1), ci_ns(0),sum(1));
u2: fadd port map(a(2),b(2), ci_ns(1),sum(2));
u3: fadd port map(a(3),b(3), ci_ns(2),sum(3));
end behavior;

BCD 加法器电路的VHDL程序
--bcdadd.vhd 1 digit bcd adder
library ieee;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(a: in std_logic_vector(3 downto 0);
        b: in std_logic_vector(3 downto 0);
        ci: in std_logic;
        co: out std_logic;
        sum: out std_logic_vector(3 downto 0));
end bcdadd;
architecture behavior of bcdadd is
signal s: std_logic_vector(3 downto 0);
signal c4: std_logic;
signal a2: std_logic_vector(3 downto 0);
signal y: std_logic;
signal zero: std_logic;
signal nouse: std_logic;
begin
u0: fadd4 port map(a,b,ci,c4,s);
y<=c4 or (s(3) and s(2)) or (s(3) and s(1));
a2<=’0’&y&y&’0’;
co<=y;
zero<=’0’;
u1: fadd4 port map(a2,s,zero,nouse,sum);
end behavior;

9补码发生器电路的VHDL程序
--com9s.vhd 9’s generator
library ieee;
use ieee.std_logic_1164.all;
entity com9s is
port( a: in std_logic_vector(3 downto 0);
        sel: in std_logic;
        z: out std_logic_vector(3 downto 0));
end com9s;
architecture behavior of com9s is
begin
  process (sel, a)
begin
     if sel=’1’ then z(3)<=(not a(3)) and (not a(2)) and (not a(1));
                             z(2)<=a(2) xor a(1);
                             z(1)<= a(1);
                             z(0)<= not a(0);
  else z<=a;
end if;
end process;
end behavior;

一个字符BCD加/减法器电路的VHDL程序
--bcd.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd is
port(a: in std_logic_vector(3 downto 0);
        b: in std_logic_vector(3 downto 0);
        ci: in std_logic;
        sel: in std_logic;
        co: out std_logic;
        sum: out std_logic_vector(3 downto 0));
end bcd;
architecture behavior of bcd is
signal b2: std_logic_vector(3 downto 0);
begin
u0:com9s port map(b,sel,b2);
u1:bcdadd port map(a,b2,ci,co,sum);
end behavior;

三个字符BCD加/减法器电路的VHDL程序
--bcd3.vhd   3 digits bcd adder/subtractor
library ieee;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(a: in std_logic_vector(11 downto 0);
        b: in std_logic_vector(11 downto 0);
        ci: in std_logic;
        sel: in std_logic;
        co: out std_logic;
        sum: out std_logic_vector(11 downto 0));
end bcd3;
architecture behavior of bcd3 is
signal cc: std_logic_vector(1 downto 0);
begin
bcd1: bcd port map (a(3 downto 0),b(3 downto 0), ci, sel, cc(0), sum(3 downto 0));
bcd2: bcd port map (a(7 downto 4),b(7 downto 4), cc(0), sel, cc(1), sum(7 downto 4));
bcd3: bcd port map (a(11 downto 8),b(11 downto 8), cc(1), sel, co, sum(11 downto 8));
end behavior;

负数取补修正电路的VHDL程序
--negative.vhd correct negative number circuit
library ieee;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port( a: in std_logic_vector(11 downto 0);
        sel: in std_logic;
        z: out std_logic_vector(11 downto 0));
end negative;
architecture behavior of negative is
signal a2: std_logic_vector(3 downto 0);
signal zero: std_logic_vector(3 downto 0);
signal unuse: std_logic;
begin
zero<=”0000”;
com1: com9s port map(a(3 downto 0), sel, a2);
bcd1:  bcdadd port map(zero, a2, sel, unuse, z(3 downto 0));
com2: com9s port map(a(7 downto 4), sel, z(7 downto 4));
com3: com9s port map(a(11 downto 8), sel, z(11 downto 8));
end behavior;


寄存器的VHDL程序
--regne.vhd n-bit register with enable
library ieee;
use ieee.std_logic_1164.all;
use work.components.all;
entity regne is
generic( n: integer:= 12);
port( r: in std_logic_vector(n-1 downto 0);
        e: in std_logic;
        clock: in std_logic;
        q: out  std_logic_vector(n-1 downto 0));
end regne;
architecture behavior of regne is
begin
   process(clock)
   begin
if clock’event and clock=’1’ then
    if e=’1’ then
       q<=r;
    end if;
end if;
end process;
end behavior;

倒数计数器VHDL程序
--downcnt.vhd  n modules downcounter
library ieee;
use ieee.std_logic_1164.all;
use work.components.all;
entity downcnt is
generic( modulus: integer:= 8);
port( clock: in std_logic;
e: in std_logic;
l: in std_logic;
q: out integer range 0 to modulus-1);
end downcnt;
architecture behavior of downcnt is
   signal count: integer range 0 to modulus-1;
begin
   process
begin
    wait until (clock’event and clock=’1’);
      if e=’1’ then
         if l=’1’ then  count<=modulus-1;
              else count<=count-1;
         end if;
      end if;
   end process;
q<=count;
end behavior;


BCD加/减法器电路VHDL程序
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee;
use ieee.std_logic_1164.all;
use work.components.all;
entity  bcd_add_sub is
port( clock: in std_logic;
        s: in std_logic;
        ea: in std_logic;
        eb: in std_logic;
dataa: in std_logic_vector(11 downto 0);
datab: in std_logic_vector(11 downto 0);
sel: in std_logic;
sum: out std_logic_vector(15 downto 0);;
done: out std_logic);
end  bcd_add_sub;
architecture behavior of bcd_add_sub is
type state_type is (s1, s2);
signal y: state_type;
signal ec: std_logic;
signal lc: std_logic;
signal z: std_logic;
signal a: std_logic_vector(11 downto 0);
signal b: std_logic_vector(11 downto 0);
signal count : integer range 0 to 7;
signal sumc: std_logic_vector(11 downto 0);
signal co: std_logic;
signal negative_com: std_logic;
begin
  fsm_transition: process(clock)
begin
     if clock’event and clock=’1’ then
          case y is
                when s1=>if z=’0’ then y<=s1;
                                               else y<=s2;  end if;
                when s2=>if s=’1’ then y<=s2;
                                               else y<=s1;  end if;
          end case;
     end if;
end process;
   fsm_output: process(y)
        begin
case y is
     when s1=> done<=’0’;
     when s2=> done<=’1’;
end case;
end process;
--datata register
rega: regne generic map(n=>12)
        port map(dataa, ea, clock, a);
   --datab register
regb: regne generic map(n=>12)
      port map(datab, eb, clock, b);
--downcounter
  ec<=’1’; lc<= not s;
  counter: downcnt generic map(modulus=>8)
      port map(clock, ec, lc, count);
   z<=’1’ when count=0 else ‘0’;
--3 word bcd add/sub circuit
bcd: bcd3 port map(a, b,sel, sel, co, sumc);
--bcd.sumc 9’s only if sel=’1’ for selecting sub mode and
--co=’0’ represent nega.sum
negative_com<=sel and (not co);
--detect minus display and encode
sum(15 downto 13)<=”000” when negative_com=’0’ else “111”;
sum(12)<=((not sel) and co);
--10’s negative sum correction circuit
com: negative port map(sumc, negative_com, sum(11 downto 0));
end behavior;


左移位寄存器电路的VHDL程序
--shiftlne.vhd n-bit right-to-left shift register
--right-to-left shift register with parallel load and enable
library ieee;
use ieee.std_logic_1164.all;
entity shiftlne is
generic( n: integer:= 7);
port(r: in std_logic_vector(n-1 downto 0);
l: in std_logic;
e: in std_logic;
w: in std_logic;
clock: in std_logic;
q: buffer std_logic_vector(n-1 downto 0));
end shiftlne;
architecture behavior of shiftlne is
begin
   process
   begin
         wait until clock’event and clock=’1’;
          if e=’1’ then
             if l=’1’ then
                  q<=r;
              else
                   q(0)<=w;
                   genbits: for i in 1 to n-1 loop
                         q(i)<=q(i-1);
                    end loop;
             end if;
         end if ;
   end process;
end behavior;



右移位寄存器电路的VHDL程序
--shiftrne.vhd n-bit left-to- right shift register
-- left-to- right shift register with parallel load and enable
library ieee;
use ieee.std_logic_1164.all;
entity shiftrne is
generic( n: integer:= 7);
port(r: in std_logic_vector(n-1 downto 0);
l: in std_logic;
e: in std_logic;
w: in std_logic;
clock: in std_logic;
q: buffer std_logic_vector(n-1 downto 0));
end shiftrne;
architecture behavior of shiftrne is
begin
   process
   begin
         wait until clock’event and clock=’1’;
          if e=’1’ then
             if l=’1’ then
                  q<=r;
              else
                   genbits: for i in 1 to n-2 loop
                         q(i)<=q(i+1);
                    end loop;
                     q(n-1)=w;
             end if;
         end if ;
   end process;
end behavior;